555 Timer

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555 Timer

The 555 Timer IC bought its title from the three 5OkΩ5KΩ resistors which are utilized in its voltage divider community. This IC is beneficial for producing correct time delays and oscillations. This chapter explains about 555 Timer intimately.

Pin Diagram and Practical Diagram

On this part, first allow us to focus on concerning the pin diagram of 555 Timer IC after which its practical diagram.

Pin Diagram

The 555 Timer IC is an eight pin mini Twin-Inline Bundle (DIP). The pin diagram of a 555 Timer IC is proven within the following determine −

Pin Diagram

The importance of every pin is self-explanatory from the above diagram. This 555 Timer IC will be operated with a DC provide of +5V to +18V. It’s primarily helpful for producing non-sinusoidal wave varieties like sq., ramp, pulse & and many others

Practical Diagram

The pictorial illustration displaying the inner particulars of a 555 Timer is called practical diagram.

The practical diagram of 555 Timer IC is proven within the following determine −

Functional Diagram

Observe that the practical diagram of 555 Timer incorporates a voltage divider community, two comparators, one SR flip-flop, two transistors and an inverter. This part discusses concerning the goal of every block or part intimately −

Voltage Divider Community

  • The voltage divider community consists of a 3 5OkΩ5KΩ resistors which are linked in sequence between the provision voltage VccVcc and floor.
  • This community offers a voltage of Vcc3Vcc3 between a degree and floor, if there exists just one 5OkΩ5KΩ resistor. Equally, it offers a voltage of 2Vcc32Vcc3 between a degree and floor, if there exists solely two 5OkΩ5KΩ resistors.

Comparator

  • The practical diagram of a 555 Timer IC consists of two comparators: an Higher Comparator (UC) and a Decrease Comparator (LC).
  • Recall {that a} comparator compares the 2 inputs which are utilized to it and produces an output.
  • If the voltage current on the non-inverting terminal of an op-amp is larger than the voltage current at its inverting terminal, then the output of comparator shall be +Vsat+Vsat. This may be thought of as Logic Excessive (‘1’) in digital illustration.
  • If the voltage current on the non-inverting terminal of op-amp is lower than or equal to the voltage at its inverting terminal, then the output of comparator shall be Vsat−Vsat. This may be thought of as Logic Low (‘0’) in digital illustration.

SR Flip-Flop

  • Recall {that a} SR flip-flop operates with both constructive clock transitions or unfavourable clock transitions. It has two inputs: S and R, and two outputs: Q(t) and Q(t)’. The outputs, Q(t) & Q(t)’ are complement to one another.
  • The next desk exhibits the state desk of a SR flip-flop
S R Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1
  • Right here, Q(t) & Q(t+1) are current state & subsequent state respectively. So, SR flip-flop can be utilized for one among these three capabilities equivalent to Maintain, Reset & Set based mostly on the enter situations, when constructive (unfavourable) transition of clock sign is utilized.
  • The outputs of Decrease Comparator (LC) and Higher Comparator (UC) are utilized as inputs of SR flip-flop as proven within the practical diagram of 555 Timer IC.

Transistors and Inverter

  • The practical diagram of a 555 Timer IC consists of 1 npn transistor Q1Q1 and one pnp transistor Q2Q2. The npn transistor Q1Q1 shall be turned ON if its base to emitter voltage is constructive and higher than cut-in voltage. In any other case, will probably be turned-OFF.
  • The pnp transistor Q2Q2 is used as buffer with a purpose to isolate the reset enter from SR flip-flop and npn transistor Q1Q1.
  • The inverter used within the practical diagram of a 555 Timer IC not solely performs the inverting motion but in addition amplifies the facility degree.

The 555 Timer IC can be utilized in mono steady operation with a purpose to produce a pulse on the output. Equally, it may be utilized in astable operation with a purpose to produce a sq. wave on the output.