Table of Contents

# Direct Sort ADCs

An Analog to Digital Converter **(ADC)** converts an analog sign right into a digital sign. The digital sign is represented with a binary code, which is a mixture of bits Zero and 1.

The **block diagram** of an ADC is proven within the following determine −

Observe that within the determine proven above, an Analog to Digital Converter **(ADC)** consists of a single analog enter and plenty of binary outputs. Basically, the variety of binary outputs of ADC might be an influence of two.

There are **two sorts** of ADCs: Direct sort ADCs and Oblique sort ADC. This chapter discusses concerning the Direct sort ADCs intimately.

If the ADC performs the analog to digital conversion immediately by using the internally generated equal digital (binary) code for evaluating with the analog enter, then it’s known as as **Direct sort ADC**.

The next are the **examples** of Direct sort ADCs −

- Counter sort ADC
- Successive Approximation ADC
- Flash sort ADC

This part discusses about these Direct sort ADCs intimately.

## Counter sort ADC

A **counter sort ADC** produces a digital output, which is roughly equal to the analog enter through the use of counter operation internally.

The **block diagram** of a counter sort ADC is proven within the following determine −

The counter sort ADC primarily consists of 5 blocks: Clock sign generator, Counter, DAC, Comparator and Management logic.

The **working** of a counter sort ADC is as follows −

- The
**management logic**resets the counter and permits the clock sign generator with the intention to ship the clock pulses to the counter, when it acquired the beginning commanding sign. - The
**counter**will get incremented by one for each clock pulse and its worth might be in binary (digital) format. This output of the counter is utilized as an enter of DAC. **DAC**converts the acquired binary (digital) enter, which is the output of counter, into an analog output. Comparator compares this analog worth,VaVa with the exterior analog enter worth ViVi.- The
**output of comparator**might be**‘1’**so long as is bigger than. The operations talked about in above two steps might be continued so long as the management logic receives ‘1’ from the output of comparator. - The
**output of comparator**might be**‘0’**when ViVi is lower than or equal to VaVa. So, the management logic receives ‘0’ from the output of comparator. Then, the management logic disables the clock sign generator in order that it doesn’t ship any clock pulse to the counter. - At this prompt, the output of the counter might be displayed because the
**digital output**. It’s nearly equal to the corresponding exterior analog enter worth ViVi.

## Successive Approximation ADC

A **successive approximation sort ADC** produces a digital output, which is roughly equal to the analog enter through the use of successive approximation method internally.

The **block diagram** of a successive approximation ADC is proven within the following determine

The successive approximation ADC primarily consists of 5 blocks− Clock sign generator, Successive Approximation Register (SAR), DAC, comparator and Management logic.

The **working** of a successive approximation ADC is as follows −

- The
**management logic**resets all of the bits of SAR and permits the clock sign generator with the intention to ship the clock pulses to SAR, when it acquired the beginning commanding sign. - The binary (digital) knowledge current in
**SAR**might be up to date for each clock pulse based mostly on the output of comparator. The output of SAR is utilized as an enter of DAC. **DAC**converts the acquired digital enter, which is the output of SAR, into an analog output. The comparator compares this analog worth VaVa with the exterior analog enter worth ViVi.- The
**output of a comparator**might be ‘1’ so long as ViVi is bigger than VaVa. Equally, the output of comparator might be ‘0’, when ViVi is lower than or equal to VaVa. - The operations talked about in above steps might be continued till the digital output is a legitimate one.

The digital output might be a legitimate one, when it’s nearly equal to the corresponding exterior analog enter worth ViVi.

## Flash sort ADC

A **flash sort ADC** produces an equal digital output for a corresponding analog enter very quickly. Therefore, flash sort ADC is the quickest ADC.

The **circuit diagram** of a 3-bit flash sort ADC is proven within the following determine −

The three-bit flash sort ADC consists of a voltage divider community, 7 comparators and a precedence encoder.

The **working** of a 3-bit flash sort ADC is as follows.

- The
**voltage divider community**comprises Eight equal resistors. A reference voltage VRVR is utilized throughout that whole community with respect to the bottom. The voltage drop throughout every resistor from backside to high with respect to floor would be the integer multiples (from 1 to eight) of VR8VR8. - The exterior
**enter voltage**ViVi is utilized to the non-inverting terminal of all comparators. The voltage drop throughout every resistor from backside to high with respect to floor is utilized to the inverting terminal of comparators from backside to high. - At a time, all of the comparators examine the exterior enter voltage with the voltage drops current on the respective different enter terminal. Which means, the comparability operations happen by every comparator
**parallelly**. - The
**output of the comparator**might be ‘1’ so long as ViVi is bigger than the voltage drop current on the respective different enter terminal. Equally, the output of comparator might be ‘0’, when, ViVi is lower than or equal to the voltage drop current on the respective different enter terminal. - All of the outputs of comparators are linked because the inputs of
**precedence encoder**.This precedence encoder produces a binary code (digital output), which is akin to the excessive precedence enter that has ‘1’. - Due to this fact, the output of precedence encoder is nothing however the binary equal
**(digital output)**of exterior analog enter voltage, ViVi.

The flash sort ADC is used within the applic