Description
Aldec ALINT-PRO one Design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which focuses on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatch, smooth and optimal synthesis, correct FSM descriptions, avoiding problems in Next design steps, clock tree problems, CDC, RDC, DFT, etc Coding for portability and reuse It is focused. Running ALINT-PRO before the RTL simulation and logic synthesis phase prevents design problems from spreading to downstream stages and reduces the number of iterations required to complete the design.
ALINT-PRO has an intuitive design framework, which features for efficient design analysis including RTL schematic view, FSM view, clock and reset view, control schematic view, dissection view, violation view, and special tools such as CDC view. , RDC view, and CDC schematics for analyzing the intersection of clock and reset domains. ALINT-PRO supports 2 different layering methods: full chip surface layering and unit layering. Both methods are complementary and are usually applied at different stages of the design cycle.
Features and facilities of Aldec ALINT-PRO program
- Analysis of clock and reset networks
- Avoid post-RTL and post-synthesis simulation mistakes
- Validation of FSM specifications
- Graphical review of extracted FSMs and specified FSM problems
- Portability and reuse of code
- Extensive CDC and RDC control with the ALDEC_CDC plugin
- CDC and RDC advanced troubleshooting environment
- Schematic view
- DFT investigations
- SDCTM support
- Extension of design constraints to describe IP
- Batch and background execution modes
required system
- Windows® 10/8.1/8/7 (64-Bit)
Pictures
Installation guide
Read the Readme.txt file in the Crack folder.
download link
Download Aldec ALINT-PRO 2021.09 x64
File(s) password: www.downloadly.ir
Size
913 MB
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