Description
VLSI CAD Part II: Layout, VLSI chip design training course with VLSI part 2 is published by Coursera Academy. A modern VLSI chip is very complex: billions of transistors, millions of logic gates used for computation and control, large blocks of memory, embedded blocks of pre-designed functions provided by third parties (called “proprietary Manavi” or IP blocks) have been designed. A suite of computer-aided design (CAD) tools takes an abstract description of the chip and refines it step-by-step to a final design.
This course focuses on the main design tools used in creating an application specific integrated circuit (ASIC) or system on chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that enable logic to layout mapping and placement, routing, and timing evaluation of large logical networks. Our goal is for students to understand how the tools themselves work at the level of fundamental algorithms and data structures. Topics covered include technology mapping, timing analysis and ASIC placement and routing.
What you will learn
- Timing analysis
- ASIC routing
VLSI CAD Part II course specifications: Layout
- Publisher: Coursera
- teacher : Rob A. Rutenbar
- English language
- Education level: Intermediate
- Number of courses: 6
- Training duration: 24 hours and 0 minutes
Chapters of VLSI CAD Part II: Layout
Course prerequisites
- Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class).
Pictures
Sample video
Installation guide
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English subtitle
Quality: 720p
download link
File(s) password: www.downloadly.ir
Size
1.15 GB
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