Description
High-Level Synthesis for FPGA, Part 3 – Advanced, course High-Level Synthesis for FPGAs, Part 3 – Advanced, is published by Udemy Academy. This course covers advanced topics in high-level synthesis (HLS) design flow. The objectives of this course are to describe, debug and implement logic circuits on FPGAs using only C/C++ language without the help of HDLs. HLS has recently been used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. HLS design flow is the future of hardware design. This topic will quickly become an essential skill for any hardware or software engineer eager to use FPGAs for their exceptional performance and low power consumption.
This course is the first to explain the advanced topics of the HLS design flow and uses the Xilinx HLS hardware and software platforms to demonstrate examples and real-world applications. During the course, we describe some examples of HLS concepts and techniques. This course includes several tests and exercises to practice and master the proposed methods and approaches. This course is the third course in the series of HLS courses on designing hardware modules and accelerating algorithms on the target FPGA. While this course focuses on multi-cycle design, advanced design, and optimization techniques in HLS, other courses in the series explain how to use single-cycle design techniques to develop combinational and sequential logic circuits in HLS.
What you will learn
- Using multi-cycle design flow to develop sequential circuits in HLS.
- Implementation of communication and flow calculation in HLS
- Using FIFO as a synchronization mechanism between connected modules
- Learn how to use an array variable inside an HLS code
- Connecting and HLS IP to BRAMs in a Vivado project
- Working with pointers in HLS
- Working with AXI protocol in HLS
- Unsupervised loop optimization in HLS
- Optimize ring flattening in HLS
- Optimize loop rotation in HLS
- Working with the HLS-Stream library in HLS
- Handshake protocol and interfaces in HLS
Who is this course suitable for?
- Hardware engineers
- Software engineers interested in FPGAs
- Lecturers, researchers and professors who want to use FPGA-based HLS in lectures, courses or research
- Digital logic enthusiasts
Specifications of the High-Level Synthesis for FPGA, Part 3 – Advanced course
- Publisher: Udemy
- teacher : Mohammad Hosseinbady
- English language
- Education level: Intermediate
- Number of courses: 58
- Training duration: 7 hours and 33 minutes
Chapters of High-Level Synthesis for FPGA, Part 3 – Advanced course
Course prerequisites
- Understanding the basic concepts of C/C++ coding
- Understanding the basic concepts of logic operators (eg, AND, OR, XOR, SHIFT)
- “High-Level Synthesis for FPGA, Part 1-Combinational Circuits” Udemy course
- “High-Level Synthesis for FPGA, Part 2 – Sequential Circuits” Udemy course
- BASYS3 evaluation board
- Xilinx Vitis-HLS and Vivado (download Vivado ML Edition or Vivado Design Suite – HLx Editions for Windows or Linux)
Pictures
Sample video
Installation guide
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download link
File(s) password: www.downloadly.ir
Size
3.52 GB
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