Download High-Level Synthesis for FPGA Part 1-Combinational Circuits

High-Level Synthesis for FPGA, Part 1-Combinational Circuits


High-Level Synthesis for FPGA, Part 1-Combinational Circuits, course High-Level Synthesis for FPGAs, Integrated Circuits Part I, is published by Udemy Academy. This course is a basic introduction to the High Level Synthesis (HLS) design stream. The objectives of this course are to describe, debug and implement combinational logic circuits on FPGAs using only C/C++ language without the help of HDLs (VHDL or Verilog). HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. The HLS design stream is the future of hardware design, which is quickly becoming a must-have skill for any hardware or software engineer eager to use FPGAs for exceptional performance and low power consumption. This course uses the Xilinx HLS hardware and software platforms to demonstrate examples and real applications.

This course is the first to build HLS design flow and skills along with digital logic circuit concepts from scratch. During the course, we describe some examples of HLS concepts and techniques. This course includes several tests and exercises to practice and master the proposed methods and approaches. This course is the first in a series of HLS courses on hardware module design and acceleration algorithms on a target FPGA. While this course focuses on combinational circuits. Other courses in this series will explain how to use HLS in the design of sequential logic circuits, algorithm acceleration, and hybrid CPU + FPGA heterogeneous systems.

What you will learn

  • Design of combined logic circuits with language ++C/C Using the HLS approach
  • Understanding the basic concepts of High Level Synthesis (HLS)
  • Using HLS concepts to design combinational logic circuits
  • HLS design flow for FPGAs
  • Work with the Xilinx Vitis-HLS and Vivado suite of tools
  • How to generate RTL hardware IPs using Vitis-HLS
  • Writing C-testbench in HLS
  • Implementation of two exciting projects with HLS

Who is this course suitable for?

  • Hardware engineers
  • Software engineers interested in FPGAs
  • Lecturers, researchers, professors who want to use FPGA-based HLS in lectures, courses or research
  • Digital logic enthusiasts

Course specifications High-Level Synthesis for FPGA, Part 1-Combinational Circuits

  • Publisher: Udemy
  • teacher : Mohammad Hosseinbady
  • English language
  • Education level: introductory
  • Number of courses: 110
  • Training duration: 7 hours and 47 minutes

Chapters of High-Level Synthesis for FPGA, Part 1-Combinational Circuits

Course prerequisites

  • Understanding the basic concepts of C/C++ coding
  • Understanding the basic concepts of logic operators (eg, AND, OR, XOR, SHIFT)
  • BASYS3 evaluation board
  • Xilinx Vitis-HLS and Vivado (download Vivado ML Edition, or Vivado Design Suite – HLx Editions for Windows or Linux)


High-Level Synthesis for FPGA, Part 1-Combinational Circuits

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Download part 1 – 2 GB

Download part 2 – 2 GB

Download part 3 – 2 GB

Download part 4 – 842 MB

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6.82 GB

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