Download Udemy – High-Level Synthesis for FPGA, Part 2 – Sequential Circuits 2022-1

High-Level Synthesis for FPGA, Part 2 - Sequential Circuits


High-Level Synthesis for FPGA, Part 2 – Sequential Circuits, course High-Level Synthesis for FPGAs, Part 2 – Sequential Circuits, published by Udemy Academy. This course is an introduction to sequential circuit design in high-level synthesis (HLS). The objectives of this course are to describe, debug and implement sequential logic circuits on FPGAs using only C/C++ language without the help of HDLs (VHDL or Verilog). In this course, Xilinx HLS software and hardware platforms are used to demonstrate examples and real applications. This course primarily uses the Xilinx Vitis-HLS toolset to describe, simulate, and synthesize a high-level design description in HDL-equivalent code. This course also explains how to use the integrated IP Logic Analyzer (ILA) in Vivado to perform real-time debugging on the Basys3 board. This course is the first of its kind to build HLS design flow and skills along with digital logic circuit concepts from scratch.

During the course, you will get to know some examples of HLS concepts and techniques. This course includes several tests and exercises to practice and master the proposed methods and approaches. In addition, the course uses three exciting projects to bring together all the concepts explained to design real circuits and hardware controllers. This course is the second course in the series of HLS courses in the design of hardware modules and acceleration algorithms on the target FPGA. While this course focuses on sequential circuits, the first course explains how to describe combinational circuits in HLS. Other courses in this series will explain how to use HLS in advanced logic circuit design, algorithm acceleration, and hybrid CPU + FPGA heterogeneous systems.

What you will learn

  • Designing sequential logic circuits with C/C++ language using HLS approach
  • Understanding the basic concepts of High Level Synthesis (HLS)
  • Using HLS concepts to design sequential logic circuits
  • HLS design flow for FPGAs
  • Working with Xilinx Vitis-HLS and Vivado design toolset
  • How to generate RTL hardware IPs using Vitis-HLS
  • Writing C-testbench in HLS
  • Implementation of three exciting projects with HLS

Who is this course suitable for?

  • Hardware engineers
  • Software engineers interested in FPGA
  • Lecturers, researchers, professors who want to use FPGA-based HLS in lectures, courses or research
    Digital logic enthusiasts

Course specifications High-Level Synthesis for FPGA, Part 2 – Sequential Circuits

  • Publisher: Udemy
  • teacher : Mohammad Hosseinbady
  • English language
  • Education level: Intermediate
  • Number of courses: 102
  • Training duration: 9 hours and 28 minutes

Chapters of High-Level Synthesis for FPGA, Part 2 – Sequential Circuits

Course prerequisites

  • Understanding the basic concepts of C/C++ coding
  • “High-Level Synthesis for FPGA, Part 1 – Combinational Circuits” course
  • BASYS3 evaluation board
  • Xilinx Vitis-HLS and Vivado toolsets


High-Level Synthesis for FPGA, Part 2 - Sequential Circuits

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Download part 1 – 2 GB

Download part 2 – 2 GB

Download part 3 – 2 GB

Download part 4 – 1.15 GB

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